IEEE Transactions on VLSI 2024 Research Papers
IEEE Transactions on VLSI 2024 Research Papers
IEEE Transactions on VLSI 2024 Research Papers, We are offering iee projects 2023-2024 in latest technology like Java, dot net, android, embedded, matlab, vlsi, hadoop, power elctronics, power system, mechanical, civil projects. IEEE Master is a unit of LeMeniz Technologies. We guide all final year M.E/M.Tech, B.E/B.Tech, MPhil, MCA, BCA, M.Sc, B.Sc, and Diploma students for their Academic Projects to get best results.
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LOW POWER
VLSI IEEE TRANSACTION LOW POWER PROJECTS 2024
| S.No | Code | Title | Year |
|---|---|---|---|
| 1 | VLSI_2024_01_LP | Soft-Error-Aware SRAM With Multinode Upset Tolerance for Aerospace Applications | 2024 |
| 2 | VLSI_2024_04_LP | An Isolated Frequency Compensation Technique for Ultra-Low-Power Low-Noise Two-Stage OTAs | 2024 |
| 3 | VLSI_2024_11_LP | Low-Cost and Highly Robust Quadruple Node Upset Tolerant Latch Design | 2024 |
| 4 | VLSI_2024_14_LP | A Wideband High-Linearity Input Buffer Based on Cascade Complementary Source Follower | 2024 |
| 5 | VLSI_2024_28_LP | An Ultra-Low Leakage and Wide-Range Voltage Level Shifter for Low-Power Digital CMOS VLSIs | 2024 |
| 6 | VLSI_2024_31_LP | The High-Efficiency Optimization Design Method for Two-Stage Miller Compensated Operational Amplifier | 2024 |
| 7 | VLSI_2024_54_LP | Exploring the Usage of Fast Carry Chains to Implement Multistage Ring Oscillators on FPGAs | 2024 |
| 8 | VLSI_2024_56_LP | A Low-Power Co-Processor to Predict Ventricular Arrhythmia for Wearable Healthcare Devices | 2024 |
AREA EFFICIENT/ TIMING & DELAY REDUCTION
VLSI IEEE TRANSACTION AE PROJECTS 2024
| S.No | Code | Title | Year |
|---|---|---|---|
| 1 | VLSI_2024_03_AE | Hardware-Efficient Logarithmic Floating-Point Multipliers for Error-Tolerant Applications | 2024 |
| 2 | VLSI_2024_05_AE | A High-Speed CRC-32 Implementation on FPGA | 2024 |
| 3 | VLSI_2024_08_AE | In-Memory Wallace Tree Multipliers Based on Majority Gates Within Voltage-Gated SOT-MRAM Crossbar Arrays | 2024 |
| 4 | VLSI_2024_12_AE | Design of a High-Performance Iterative Barrett Modular Multiplier for Crypto Systems | 2024 |
| 5 | VLSI_2024_13_AE | A High-Performance Transparent Memory Data Encryption and Authentication Scheme Based on Ascon Cipher | 2024 |
| 6 | VLSI_2024_22_AE | VLSI Architectures and Hardware Implementation of Ultra Low-Latency Pietra-Ricci Index Detector | 2024 |
| 7 | VLSI_2024_23_AE | Flexible FPGA Gaussian Random Number Generators With Reconfigurable Variance | 2024 |
| 8 | VLSI_2024_25_AE | A 32-Bit Ripple-Ling Hybrid Carry Adder | 2024 |
| 9 | VLSI_2024_27_AE | A Reconfigurable Processing Element for Multiple-Precision Floating/Fixed-Point HPC | 2024 |
| 10 | VLSI_2024_39_AE | A Novel Design of High Speed Multiplier Using Hybrid Adder Technique | 2024 |
| 11 | VLSI_2024_40_AE | Efficient Pseudo Random Number Generator (PRNG) Design on FPGA | 2024 |
| 12 | VLSI_2024_41_AE | Factored Systolic Arrays Based on Radix-8 Multiplication for Machine Learning Acceleration | 2024 |
| 13 | VLSI_2024_46_AE | Algebraic Implementation of Extended Finite State Machine Networks | 2024 |
| 14 | VLSI_2024_47_AE | Efficient Approximate Floating-Point Multiplier With Runtime Reconfigurable Frequency and Precision | 2024 |
| 15 | VLSI_2024_49_AE | Accumulator-Based 16-Bit Processor for Wireless Sensor Nodes | 2024 |
| 16 | VLSI_2024_51_AE | Low-Precision Mixed-Computation Models for Inference on Edge | 2024 |
| 17 | VLSI_2024_52_AE | A High Speed and Area Efficient Processor for Elliptic Curve Scalar Point Multiplication | 2024 |
| 18 | VLSI_2024_53_AE | HRM: M-Term Heterogeneous Hybrid Blend Recursive Multiplier for GF(2n) Polynomial | 2024 |
| 19 | VLSI_2024_57_AE | FELIX: FPGA-Based Scalable and Lightweight Accelerator for Large Integer Extended GCD | 2024 |
| 20 | VLSI_2024_58_AE | Low-Complexity Parallel Chien Search Architecture Based on Vandermonde Matrix Decomposition | 2024 |
HIGH SPEED DATA TRANSMISSION
VLSI IEEE TRANSACTION HS PROJECTS 2024
| S.No | Code | Title | Year |
|---|---|---|---|
| 1 | VLSI_2024_02_HS | Variable Conversion Approach for Design Optimization of Low-Voltage Low-Pass Filters | 2024 |
| 2 | VLSI_2024_06_HS | A 35-Gb/s PAM-4 Transmitter With 7B4Q Full-Transition Avoidance | 2024 |
| 3 | VLSI_2024_09_HS | Memory-Efficient Multiplier-Less 2-D DWT Design for Wireless Visual Sensors | 2024 |
| 4 | VLSI_2024_10_HS | A Novel Design Approach and VLSI Architecture of Rationalized Bi-Orthogonal Wavelet Filter Banks | 2024 |
| 5 | VLSI_2024_15_HS | On the Use of FIR Feedback in Bandpass Delta-Sigma Modulators | 2024 |
| 6 | VLSI_2024_16_HS | Fast FPGA Prototyping to Explore and Compare New SPWM Strategies | 2024 |
| 7 | VLSI_2024_17_HS | Kalman Filters Based Distributed Cyber-Attack Mitigation Layers for DC Microgrids | 2024 |
| 8 | VLSI_2024_18_HS | A 0.14-nJ/b 200-Mb/s Quasi-Balanced FSK Transceiver | 2024 |
| 9 | VLSI_2024_24_HS | Theory and Low-Power Design of Moving Accumulative Sign Filter | 2024 |
| 10 | VLSI_2024_26_HS | Integrating OFDM Into Switching Power Supplies for Visible Light Communications | 2024 |
| 11 | VLSI_2024_29_HS | A Low-Power and Low-Latency Speech Feature Extractor | 2024 |
| 12 | VLSI_2024_32_HS | A New Design of Low Hardware Cost and Low Power Programmable FIR Filters | 2024 |
| 13 | VLSI_2024_33_HS | DFT-Based Method for Accurate I/Q Imbalance Estimation | 2024 |
| 14 | VLSI_2024_37_HS | FPGA Implementation of Correlator for DSSS Systems | 2024 |
| 15 | VLSI_2024_42_HS | A Check-and-Balance Scheme in Multiphase Delay-Locked Loop | 2024 |
| 16 | VLSI_2024_43_HS | Fractionally-Spaced Equalizers as Clock and Data Recovery Loops | 2024 |
| 17 | VLSI_2024_44_HS | A 71.2-μW Speech Recognition Accelerator With Recurrent Spiking Neural Network | 2024 |
| 18 | VLSI_2024_45_HS | A New ISA for High-Speed and Area-Efficient ALPG | 2024 |
| 19 | VLSI_2024_50_HS | Low Complexity Design of Logistic Distance Metric Adaptive Filter | 2024 |
| 20 | VLSI_2024_55_HS | High-Throughput Bilinear Pairing Processor for Server-Side FPGA Applications | 2024 |
| 21 | VLSI_2024_59_HS | Designing Low-Power RISC-V Multicore Processors for IoT Endnodes | 2024 |
VLSI Design of Image, Video and Audio Processing
VLSI IEEE TRANSACTION IM PROJECTS 2024
| S.No | Code | Title | Year |
|---|---|---|---|
| 1 | VLSI_2024_19_IM | HDSuper: High-Quality and High Computational Utilization Edge Super-Resolution Accelerator With Hardware-Algorithm Co-Design Techniques | 2024 |
| 2 | VLSI_2024_20_IM | ESSR: An 8K@30FPS Super-Resolution Accelerator With Edge Selective Network | 2024 |
| 3 | VLSI_2024_21_IM | ACE-CNN: Approximate Carry Disregard Multipliers for Energy-Efficient CNN-Based Image Classification | 2024 |
| 4 | VLSI_2024_30_IM | Logarithmically Optimized Real-Time HDR Tone Mapping With Hardware Implementation | 2024 |
| 5 | VLSI_2024_34_IM | A Low Cost FPGA Implementation of Retinex Based Low-Light Image Enhancement Algorithm | 2024 |
| 6 | VLSI_2024_34_IM | A Low Complexity JPEG Coding System | 2024 |
| 7 | VLSI_2024_36_IM | A High-Speed Computational Pipeline Single MAC-Based VLSI Architecture for Real-Time Signal and Image Processing | 2024 |
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