IEEE Transactions on VLSI 2024 Research Papers
IEEE Transactions on VLSI 2024 Research Papers
IEEE Transactions on VLSI 2024 Research Papers, We are offering iee projects 2023-2024 in latest technology like Java, dot net, android, embedded, matlab, vlsi, hadoop, power elctronics, power system, mechanical, civil projects. IEEE Master is a unit of LeMeniz Technologies. We guide all final year M.E/M.Tech, B.E/B.Tech, MPhil, MCA, BCA, M.Sc, B.Sc, and Diploma students for their Academic Projects to get best results.
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LOW POWER
| S.No | Code | Title | Year |
|---|---|---|---|
| 1 | VLSI_2024_01_LP | Soft-Error-Aware SRAM With Multinode Upset Tolerance for Aerospace Applications Proposes a soft-error-resilient SRAM architecture designed for aerospace systems. Uses multinode upset correction techniques to improve memory reliability under radiation exposure. |
2024 |
| 2 | VLSI_2024_04_LP | An Isolated Frequency Compensation Technique for Ultra-Low-Power Low-Noise Two-Stage OTAs Introduces a frequency compensation method for two-stage OTAs to reduce noise and power consumption. Enhances stability in analog circuit design. |
2024 |
| 3 | VLSI_2024_11_LP | Low-Cost and Highly Robust Quadruple Node Upset Tolerant Latch Design Presents a latch design resistant to multiple-node upsets with improved robustness. Optimized for low-cost and reliable digital systems. |
2024 |
| 4 | VLSI_2024_14_LP | A Wideband High-linearity Input Buffer Based on Cascade Complementary Source Follower Designs a wideband input buffer with high linearity using cascaded source followers. Suitable for high-speed analog front-end systems. |
2024 |
| 5 | VLSI_2024_28_LP | An Ultra-Low Leakage and Wide-Range Voltage Level Shifter for Low-Power Digital CMOS VLSIs Proposes a level shifter with ultra-low leakage current for CMOS VLSI systems. Supports wide voltage scaling in low-power designs. |
2024 |
| 6 | VLSI_2024_31_LP | The High-Efficiency Optimization Design Method for Two-Stage Miller Compensated Operational Amplifier Optimizes Miller-compensated operational amplifiers for improved efficiency and stability. Reduces power while maintaining gain performance. |
2024 |
| 7 | VLSI_2024_54_LP | Exploring the Usage of Fast Carry Chains to Implement Multistage Ring Oscillators on FPGAs: Design and Characterization Investigates FPGA carry chains for implementing ring oscillators. Improves timing accuracy and hardware characterization methods. |
2024 |
| 8 | VLSI_2024_56_LP | A Low-Power Co-Processor to Predict Ventricular Arrhythmia for Wearable Healthcare Devices Develops a low-power ECG co-processor for arrhythmia prediction in wearable devices. Optimized for real-time medical monitoring. |
2024 |
AREA EFFICIENT/ TIMING & DELAY REDUCTION
| S.No | Code | Title | Year |
|---|---|---|---|
| 1 | VLSI_2024_03_AE | Hardware-Efficient Logarithmic Floating-Point Multipliers for Error-Tolerant Applications Proposes a logarithmic-based floating-point multiplier architecture that reduces hardware complexity. Designed for error-tolerant computing with improved area and power efficiency. |
2024 |
| 2 | VLSI_2024_05_AE | A high-speed CRC-32 Implementation on FPGA Implements a high-throughput CRC-32 hardware architecture optimized for FPGA platforms. Achieves faster error detection with pipelined computation. |
2024 |
| 3 | VLSI_2024_08_AE | In-Memory Wallace Tree Multipliers Based on Majority Gates Within Voltage-Gated SOT-MRAM Crossbar Arrays Introduces an in-memory computing multiplier using SOT-MRAM crossbars. Utilizes majority logic for efficient Wallace tree multiplication. |
2024 |
| 4 | VLSI_2024_12_AE | Design of a High-Performance Iterative Barrett Modular Multiplier for Crypto Systems Presents a modular multiplier based on Barrett reduction for cryptographic applications. Improves speed and hardware utilization in secure systems. |
2024 |
| 5 | VLSI_2024_13_AE | A High-Performance Transparent Memory Data Encryption and Authentication Scheme Based on Ascon Cipher Implements lightweight Ascon-based encryption for memory systems. Provides secure authentication with minimal hardware overhead. |
2024 |
| 6 | VLSI_2024_22_AE | VLSI Architectures and Hardware Implementation of Ultra Low-Latency and Area-Efficient Pietra-Ricci Index Detector for Spectrum Sensing Designs a spectrum sensing hardware accelerator for communication systems. Reduces latency and area while maintaining detection accuracy. |
2024 |
| 7 | VLSI_2024_23_AE | Flexible FPGA Gaussian Random Number Generators With Reconfigurable Variance Proposes a configurable Gaussian random number generator for FPGA systems. Supports variable variance for stochastic applications. |
2024 |
| 8 | VLSI_2024_25_AE | A 32-Bit Ripple-Ling Hybrid Carry Adder Introduces a hybrid carry adder architecture combining ripple and carry techniques. Improves speed and reduces propagation delay. |
2024 |
| 9 | VLSI_2024_27_AE | A Reconfigurable Processing Element for Multiple-Precision Floating/Fixed-Point HPC Designs a flexible processing element supporting multiple precision formats. Optimized for high-performance computing workloads. |
2024 |
| 10 | VLSI_2024_39_AE | A Novel Design of High Speed Multiplier Using Hybrid Adder Technique Proposes a high-speed multiplier using hybrid adder optimization. Reduces critical path delay for arithmetic units. |
2024 |
| 11 | VLSI_2024_40_AE | Efficient Pseudo Random Number Generator (PRNG) Design on FPGA Implements a lightweight PRNG architecture optimized for FPGA platforms. Suitable for cryptographic and simulation applications. |
2024 |
| 12 | VLSI_2024_41_AE | Factored Systolic Arrays Based on Radix-8 Multiplication for Machine Learning Acceleration Presents systolic array architecture optimized for ML acceleration. Uses radix-8 multiplication for improved throughput. |
2024 |
| 13 | VLSI_2024_46_AE | Algebraic Implementation of Extended Finite State Machine Networks Introduces algebraic modeling techniques for FSM network implementation. Improves scalability and hardware mapping efficiency. |
2024 |
| 14 | VLSI_2024_47_AE | Efficient Approximate Floating-Point Multiplier With Runtime Reconfigurable Frequency and Precision Proposes an approximate multiplier with runtime reconfigurability. Balances accuracy, frequency, and energy efficiency. |
2024 |
| 15 | VLSI_2024_49_AE | Accumulator-Based 16-Bit Processor for Wireless Sensor Nodes Designs a compact 16-bit processor optimized for sensor node applications. Focuses on ultra-low power and efficient accumulation operations. |
2024 |
| 16 | VLSI_2024_51_AE | Low-Precision Mixed-Computation Models for Inference on Edge Introduces mixed-precision computation models for edge inference. Reduces memory and power usage while maintaining accuracy. |
2024 |
| 17 | VLSI_2024_52_AE | A High Speed and Area Efficient Processor for Elliptic Curve Scalar Point Multiplication for GF(2m) Implements an ECC scalar multiplication processor optimized for GF(2m). Achieves high speed with reduced area consumption. |
2024 |
| 18 | VLSI_2024_53_AE | HRM: M-Term Heterogeneous Hybrid Blend Recursive Multiplier for GF(2n) Polynomial Proposes a recursive multiplier for GF(2n) polynomial arithmetic. Optimized for cryptographic hardware acceleration. |
2024 |
| 19 | VLSI_2024_57_AE | FELIX: FPGA-Based Scalable and Lightweight Accelerator for Large Integer Extended GCD Introduces an FPGA accelerator for extended GCD computation. Designed for cryptographic and number theory applications. |
2024 |
| 20 | VLSI_2024_58_AE | Low-Complexity Parallel Chien Search Architecture Based on Vandermonde Matrix Decomposition Presents a parallel Chien search architecture for error-correcting codes. Reduces computational complexity using matrix decomposition. |
2024 |
HIGH SPEED DATA TRANSMISSION
| S.No | Code | Title | Year |
|---|---|---|---|
| 1 | VLSI_2024_02_HS | Variable Conversion Approach for Design Optimization of Low-Voltage Low-Pass Filters Proposes a variable conversion technique to optimize low-voltage low-pass filter design. Reduces power consumption while maintaining signal integrity. |
2024 |
| 2 | VLSI_2024_06_HS | A 35-Gb/s PAM-4 Transmitter With 7B4Q Full-Transition Avoidance and Area-Efficient Gm-Boosting Techniques Designs a high-speed PAM-4 transmitter optimized for 35 Gb/s operation. Uses transition-avoidance coding and gm-boosting for efficiency. |
2024 |
| 3 | VLSI_2024_09_HS | Memory-Efficient Multiplier-Less 2-D DWT Design Using Combined Convolution and Lifting Schemes for Wireless Visual Sensors Presents a multiplier-less 2D DWT architecture for wireless sensors. Reduces memory usage using hybrid lifting and convolution techniques. |
2024 |
| 4 | VLSI_2024_10_HS | A Novel Design Approach and VLSI Architecture of Rationalized Bi-Orthogonal Wavelet Filter Banks Introduces optimized wavelet filter bank architecture for signal processing. Improves computational efficiency and hardware utilization. |
2024 |
| 5 | VLSI_2024_15_HS | On the Use of FIR Feedback in Bandpass Delta-Sigma Modulators Analyzes FIR feedback techniques in delta-sigma modulators. Enhances stability and noise shaping performance. |
2024 |
| 6 | VLSI_2024_16_HS | Fast FPGA Prototyping to Explore and Compare New SPWM Strategies Develops FPGA-based rapid prototyping for SPWM strategies. Enables fast comparison of modulation techniques. |
2024 |
| 7 | VLSI_2024_17_HS | Kalman Filters Based Distributed Cyber-Attack Mitigation Layers for DC Microgrids Uses Kalman filtering to detect and mitigate cyber-attacks in DC microgrids. Improves system resilience and stability. |
2024 |
| 8 | VLSI_2024_18_HS | A 0.14-nJ/b 200-Mb/s 2.7–3.5-GHz Quasi-Balanced FSK Transceiver With PLL-Based Modulation and Sideband Energy Detection Implements an ultra-low-power FSK transceiver with PLL-based modulation. Optimized for energy-efficient wireless communication. |
2024 |
| 9 | VLSI_2024_24_HS | Theory and Low-Power Design of Moving Accumulative Sign Filter Proposes a low-power filter architecture based on accumulative sign processing. Suitable for real-time signal applications. |
2024 |
| 10 | VLSI_2024_26_HS | Integrating OFDM Into Switching Power Supplies for Visible Light Communications Explores OFDM integration into power supply systems for VLC applications. Improves data transmission efficiency via lighting systems. |
2024 |
| 11 | VLSI_2024_29_HS | A Low-Power and Low-Latency Speech Feature Extractor Based on Time-Domain Filter Bank Designs a speech feature extraction system using time-domain filter banks. Focuses on low power and real-time processing. |
2024 |
| 12 | VLSI_2024_32_HS | A New Design of Low Hardware Cost and Low Power Programmable FIR Filters Presents a programmable FIR filter architecture optimized for low hardware cost and energy efficiency. |
2024 |
| 13 | VLSI_2024_33_HS | DFT-Based Method for Accurate I/Q Imbalance Estimation Introduces a DFT-based method for precise I/Q imbalance estimation in communication systems. |
2024 |
| 14 | VLSI_2024_37_HS | FPGA Implementation of Correlator for Direct Sequence Spread Spectrum (DSSS) Systems Implements DSSS correlator on FPGA for wireless communication systems. Enhances signal detection performance. |
2024 |
| 15 | VLSI_2024_42_HS | A Check-and-Balance Scheme in Multiphase Delay-Locked Loop Proposes stability improvement techniques for DLL systems. Enhances phase alignment accuracy. |
2024 |
| 16 | VLSI_2024_43_HS | Fractionally-Spaced Equalizers as Clock and Data Recovery Loops Uses fractionally spaced equalizers for clock and data recovery. Improves communication robustness. |
2024 |
| 17 | VLSI_2024_44_HS | A 71.2-μW Speech Recognition Accelerator With Recurrent Spiking Neural Network Designs ultra-low-power speech recognition hardware using spiking neural networks. Optimized for wearable AI devices. |
2024 |
| 18 | VLSI_2024_45_HS | A New ISA for High-Speed and Area-Efficient ALPG Introduces a new instruction set architecture for ALPG systems. Improves execution speed and hardware efficiency. |
2024 |
| 19 | VLSI_2024_50_HS | Low Complexity Design of Logistic Distance Metric Adaptive Filter for Impulsive Noise Environments Proposes adaptive filtering technique for impulsive noise reduction. Reduces computational complexity significantly. |
2024 |
| 20 | VLSI_2024_55_HS | High-Throughput Bilinear Pairing Processor for Server-Side FPGA Applications Implements high-speed bilinear pairing processor for cryptographic server workloads. Optimized for FPGA acceleration. |
2024 |
| 21 | VLSI_2024_59_HS | Designing Low-Power RISC-V Multicore Processors With a Shared Lightweight Floating Point Unit for IoT Endnodes Presents a low-power RISC-V multicore architecture with shared FPU. Designed for IoT edge computing applications. |
2024 |
VLSI Design of Image, Video and Audio Processing
| S.No | Code | Title | Year |
|---|---|---|---|
| 1 | VLSI_2024_19_IM | HDSuper: High-Quality and High Computational Utilization Edge Super-Resolution Accelerator With Hardware-Algorithm Co-Design Techniques Proposes a hardware-algorithm co-designed super-resolution accelerator for edge devices. Improves image quality while maximizing hardware utilization efficiency. |
2024 |
| 2 | VLSI_2024_20_IM | ESSR: An 8K@30FPS Super-Resolution Accelerator With Edge Selective Network Designs an edge-selective neural network accelerator for real-time 8K super-resolution processing. Optimized for high throughput and low latency. |
2024 |
| 3 | VLSI_2024_21_IM | ACE-CNN: Approximate Carry Disregard Multipliers for Energy-Efficient CNN-Based Image Classification Introduces approximate multiplier architecture for CNN inference. Reduces power consumption while maintaining classification accuracy. |
2024 |
| 4 | VLSI_2024_30_IM | Logarithmically Optimized Real-Time HDR Tone Mapping With Hardware Implementation Presents a hardware-efficient HDR tone mapping system using logarithmic optimization techniques. Enables real-time image enhancement. |
2024 |
| 5 | VLSI_2024_34_IM | A Low Cost FPGA Implementation of Retinex Based Low-Light Image Enhancement Algorithm Implements Retinex-based image enhancement on FPGA for low-light conditions. Optimized for cost-effective real-time processing. |
2024 |
| 6 | VLSI_2024_34_IM (2) | A low complexity JPEG coding system Proposes a simplified JPEG encoding architecture for reduced hardware complexity. Maintains acceptable compression quality with low resource usage. |
2024 |
| 7 | VLSI_2024_36_IM | A High-Speed Computational Pipeline Single MAC-Based VLSI Architecture for Real-Time Signal and Image Processing Designs a pipelined single-MAC architecture for real-time signal and image processing tasks. Improves speed and hardware efficiency. |
2024 |
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