IEEE Transactions on VLSI 2026 Research Papers
IEEE Transactions on VLSI 2025 Research Papers
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LOW POWER
VLSI IEEE TRANSACTION LOW POWER PROJECTS 2025
| S.No | Code | Title | Year |
|---|---|---|---|
| 1 | VLSI_2025_01_LP | 46-nA High-PSR CMOS Buffered Voltage Reference With 1.2–5 V and -40°C to 125°C Operating Range | 2025 |
| 2 | VLSI_2025_11_LP | Exploiting Body-Driven Feedbacks in Physical Unclonable Functions for Ultra Low Voltage Applications | 2025 |
| 3 | VLSI_2025_17_LP | Cryogenic Front-End ASICs for Low-Noise Readout of Charge Signals | 2025 |
| 4 | VLSI_2025_35_LP | Low-Power and High-Speed SRAM Cells With Double-Node Upset Self-Recovery | 2025 |
| 5 | VLSI_2025_37_LP | A Single-Ended High-Voltage-Compliant 11-bit Current-Steering DAC | 2025 |
| 6 | VLSI_2025_45_LP | Leveraging Highly Approximated Multipliers in DNN Inference | 2025 |
| 7 | VLSI_2025_47_LP | Design of a Hardware-Efficient Approximate 4-2 Compressor | 2025 |
| 8 | VLSI_2025_54_LP | A Laddered-Inverter Nonoverlapping Clock Generator | 2025 |
| 9 | VLSI_2025_55_LP | An Area-Efficient VLSI Architecture for High-Throughput Computation of the 2-D DWT | 2025 |
| 10 | VLSI_2025_57_LP | A Two-Stage CMOS Amplifier With High Degree of Stability | 2025 |
| 11 | VLSI_2025_58_LP | Revisiting Multiple ECC on High-Density NAND Flash Memory | 2025 |
| 12 | VLSI_2025_60_LP | A Nanopower EEG Low-Pass Filter Using Current-Sharing Vertical Differential Pairs | 2025 |
| 13 | VLSI_2025_76_LP | High Efficiency Multiply-Accumulator Using Ternary Logic | 2025 |
| 14 | VLSI_2025_77_LP | Low-Power Subthreshold Voltage References for High-Temperature Applications | 2025 |
| 15 | VLSI_2025_84_LP | Low-Power High Precision Floating-Point Divider With Bidimensional Linear Approximation | 2025 |
| 16 | VLSI_2025_85_LP | Fanout-Based Reliability Model for SER Estimation in Combinational Circuits | 2025 |
AREA EFFICIENT/ TIMING & DELAY REDUCTION
VLSI IEEE TRANSACTION AE PROJECTS 2025
| S.No | Code | Title | Year |
|---|---|---|---|
| 1 | VLSI_2025_05_AE | Manipulated Lookup Table Method for Efficient High-Performance Modular Multiplier | 2025 |
| 2 | VLSI_2025_06_AE | Low-Power High Precision Floating-Point Divider With Bidimensional Linear Approximation | 2025 |
| 3 | VLSI_2025_08_AE | Leveraging Highly Approximated Multipliers in DNN Inference | 2025 |
| 4 | VLSI_2025_09_AE | Hardware Implementation of Improved Banker’s Fixed-Point Rounding Algorithm | 2025 |
| 5 | VLSI_2025_10_AE | Fail-Safe Logic Design Strategies Within Modern FPGA Architectures | 2025 |
| 6 | VLSI_2025_12_AE | Enhancing Delay-Driven LUT Mapping With Boolean Decomposition | 2025 |
| 7 | VLSI_2025_14_AE | Embedded Hardware-Efficient FPGA Architecture for SVM Learning and Inference | 2025 |
| 8 | VLSI_2025_16_AE | Design and Analysis of Energy Efficient Approximate Multipliers | 2025 |
| 9 | VLSI_2025_18_AE | C4TERO: Configurable Cascaded Carry Chains for High Reliability TERO PUFs | 2025 |
| 10 | VLSI_2025_19_AE | AXI Hardware Accelerator for McEliece on FPGA Embedded Systems | 2025 |
| 11 | VLSI_2025_23_AE | A High-Resolution Calibration Method for Time-to-Digital Converter of Lidar | 2025 |
| 12 | VLSI_2025_24_AE | Energy-Efficient Syndrome Calculation Architecture for BCH Decoders | 2025 |
| 13 | VLSI_2025_25_AE | Low-Complexity Implementation of Real-Time Reconfigurable Low-Pass Equalizers | 2025 |
| 14 | VLSI_2025_26_AE | MSDF-Based MAC for Energy-Efficient Neural Networks | 2025 |
| 15 | VLSI_2025_27_AE | A Study of Signed-Digit Hybrid Stochastic Number for Arithmetic Computing | 2025 |
| 16 | VLSI_2025_28_AE | Manipulated Lookup Table Method for Efficient High-Performance Modular Multiplier | 2025 |
| 17 | VLSI_2025_29_AE | SPEED: A Scalable RISC-V Vector Processor | 2025 |
| 18 | VLSI_2025_30_AE | FPGA-Based Low-Bit and Lightweight Fast Light Field Depth Estimation | 2025 |
| 19 | VLSI_2025_31_AE | A Comparative Analysis of Low Temperature and Room Temperature Circuit Operation | 2025 |
| 20 | VLSI_2025_39_AE | A 4.86-pJ/b Energy-Efficient Fully Parallel Stochastic LDPC Decoder | 2025 |
| 21 | VLSI_2025_40_AE | A Pay-Per-ISE RISC-V Processor With Hardware-Assisted Orthogonal Obfuscation | 2025 |
| 22 | VLSI_2025_48_AE | An Efficient Test Architecture Using Hybrid Built-In Self-Test | 2025 |
| 23 | VLSI_2025_53_AE | Strassen Multisystolic Array Hardware Architectures | 2025 |
| 24 | VLSI_2025_61_AE | High-Speed Compute-Efficient Bandit Learning for Many Arms | 2025 |
| 25 | VLSI_2025_62_AE | Design of Low-Cost and High-Accurate 8-bit Logarithmic Floating-Point Arithmetic Circuits | 2025 |
| 26 | VLSI_2025_63_AE | An Area-Energy-Efficient 64–2048 Point FFT | 2025 |
| 27 | VLSI_2025_69_AE | A Reconfigurable Floating-Point Division and Square Root Architecture | 2025 |
| 28 | VLSI_2025_81_AE | In-Memory Implementation of an Approximate Adder With Reduced Latency | 2025 |
| 29 | VLSI_2025_82_AE | RIVL: A Low-Cost SoC Agile Development Platform for RISC-V | 2025 |
HIGH SPEED DATA TRANSMISSION
VLSI IEEE TRANSACTION HS PROJECTS 2026
| S.No | Code | Title | Year |
|---|---|---|---|
| 1 | VLSI_2025_02_HS | Scalable 5G NR Rate-Matcher and Rate-Dematcher for Efficient Use in FPGA Accelerators | 2025 |
| 2 | VLSI_2025_04_HS | Method to Determine Quantization-Related Parameters of the Digital-to-Time Converter | 2025 |
| 3 | VLSI_2025_07_HS | Longest-First Search Using Bloom Filter: Algorithm and FPGA Implementation | 2025 |
| 4 | VLSI_2025_13_HS | Enhanced Fetal Arrhythmia Classification by Non-Invasive ECG | 2025 |
| 5 | VLSI_2025_15_HS | Design and HDL Implementation of Pulse-Arrival-Time Estimation | 2025 |
| 6 | VLSI_2025_20_HS | Analysis and Mitigation of Excess Phase Noise and Spurs | 2025 |
| 7 | VLSI_2025_21_HS | Advanced Quantization Schemes for FFT Architectures | 2025 |
| 8 | VLSI_2025_22_HS | A Hybrid Speech Enhancement Technique Based on DWT | 2025 |
| 9 | VLSI_2025_33_HS | ReAdapt-II: Energy-Quality Optimizations for VLSI Adaptive Filters | 2025 |
| 10 | VLSI_2025_37_HS | FANNS: An FPGA-Based Approximate Nearest-Neighbor Search Accelerator | 2025 |
| 11 | VLSI_2025_41_HS | Adjacent Channel Weight Dependable RLS Adaptive Filter | 2025 |
| 12 | VLSI_2025_42_HS | An Energy-Efficient Configurable 1-D CNN-Based ECG Classification Coprocessor | 2025 |
| 13 | VLSI_2025_43_HS | A Hybrid Speech Enhancement Technique Based on DWT and Spectral Subtraction | 2025 |
| 14 | VLSI_2025_44_HS | An Area-Efficient VLSI Architecture for High-Throughput Computation of the 2-D DWT | 2025 |
| 15 | VLSI_2025_46_HS | AdAM: Adaptive Approximate Multiplier for Fault Tolerance | 2025 |
| 16 | VLSI_2025_48_HS | Fault Bounding On-Die BCH Codes for Improving Reliability | 2025 |
| 17 | VLSI_2025_50_HS | A 7.4–9.2-GHz Fractional-N Differential Sampling PLL | 2025 |
| 18 | VLSI_2025_51_HS | Area-Efficient Pipeline Architecture for Serial FFT | 2025 |
| 19 | VLSI_2025_52_HS | ATEP: An Asynchronous Timing Error Prediction Circuit | 2025 |
| 20 | VLSI_2025_55_HS | An Area-Efficient VLSI Architecture for High-Throughput 2-D DWT | 2025 |
| 21 | VLSI_2025_59_HS | A 25-GHz PLL Achieving 8-ns Phase-Shifting Time | 2025 |
| 22 | VLSI_2025_64_HS | A Sub-0.9-ps Static Phase Offset 500 MHz Delay-Locked Loop | 2025 |
| 23 | VLSI_2025_66_HS | Toward High-Performance Network Coding: FPGA Acceleration | 2025 |
| 24 | VLSI_2025_67_HS | An Implementation Method for 100% ASK Modulation Applied to NFC Tags | 2025 |
| 25 | VLSI_2025_68_HS | A Low-Latency Feed-Forward Architecture for Image Filtering | 2025 |
| 26 | VLSI_2025_72_HS | Optimized Algorithms for FPGA Implementation of PDCCH Chain for 5G-NR | 2025 |
| 27 | VLSI_2025_73_HS | Low-Complexity Continuously Variable Digital Filter | 2025 |
| 28 | VLSI_2025_83_HS | VLSI Architecture Design for Compact Shortcut Denoising Autoencoder Neural Network | 2025 |
VLSI Design of Image, Video and Audio Processing
VLSI IEEE TRANSACTION IM PROJECTS 2025
| S.No | Code | Title | Year |
|---|---|---|---|
| 1 | VLSI_2025_03_IM | NN2FPGA: Optimizing CNN Inference on FPGAs With Binary Integer Programming | 2025 |
| 2 | VLSI_2025_32_IM | Detect and Replace: Efficient Soft Error Protection of FPGA-Based CNN Accelerators | 2025 |
| 3 | VLSI_2025_34_IM | Research on Hardware Acceleration of Traffic Sign Recognition Based on Spiking Neural Network | 2025 |
| 4 | VLSI_2025_36_IM | An Interpolation-Free Fractional Motion Estimation Algorithm and Hardware Implementation for VVC | 2025 |
| 5 | VLSI_2025_65_IM | Design of a Low-Power Analog Integrated Deep Convolutional Neural Network | 2025 |
| 6 | VLSI_2025_70_IM | Hardware-Efficient Architecture for Multiple Quantized Gaussian Noise Generation | 2025 |
| 7 | VLSI_2025_74_IM | MBS: A High-Precision Approximation Method for Softmax and Efficient Hardware Implementation | 2025 |
| 8 | VLSI_2025_75_IM | EdgeLLM: A Highly Efficient CPU-FPGA Heterogeneous Edge Accelerator for Large Language Models | 2025 |
| 9 | VLSI_2025_78_IM | A High-Throughput FPGA Accelerator for Lightweight CNNs With Balanced Dataflow | 2025 |
| 10 | VLSI_2025_79_IM | A Novel Transform Accelerator With Fast Kernel Selection and Efficient Transform Circuit | 2025 |
| 11 | VLSI_2025_80_IM | Rational-Exponent Filters with Applications to Generalized Exponent Filters | 2025 |
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