A nanopower, buffered CMOS voltage reference designed to operate across the entire industrial temperature range (from −40 ◦C to 125 ◦C) and with an input voltage range from 1.2 to 5 V (automotive applications) is presented. The solution provides 390 mV at 20 ◦C and is implemented in a standard BCD technology featuring 160-nm CMOS devices. It is characterized by an average temperature coefficient of 200 ppm/◦C, a line sensitivity (LS) of 0.138%/V, and a power supply rejection of −83 dB at 100 Hz. In addition, the circuit occupies a die area of 0.146 mm2 (with the reference circuit alone covering 0.043 mm2 ) and maintains a highly stable current consumption of around 45 nA across various process and input voltage conditions (25 nA for the reference circuit alone) while providing a maximum output current of 630 µA with a load regulation of 0.016 mV/µA..

This paper introduces an innovative approach to designing a mismatched current mirror with a fully unbalanced output, significantly reducing the minimum supply voltage requirements for Regulated Cascode Current Mirror (RCCM) Physical Unclonable Functions (PUFs). Leveraging body-driven feedback mechanisms, the proposed circuit reliably operates with supply voltages as low as 0.3V, maintaining stable power consumption through a reference bias current. The resulting PUF achieves remarkable energy efficiency, consuming only 0.3 fJ per bit, without compromising statistical performance. It exhibits a response bias of 49.42%, a reliability of 99.483%, and a uniqueness of 50.176%. Validation of this novel approach is conducted through simulations and measurements on a 130nm CMOS test-chip, considering a nominal supply voltage of 0.3V, ±10% supply voltage variations, and a temperature range from 0 ◦C to 75◦C. Rigorous experimental verification on 20 chip samples, along with detailed explanations of design methodologies, underscores the robustness and practicality of the proposed Body-PUF design. Comparative analyses against state-of-the-art literature reveal that the Body-PUF outperforms previous PUF designs in Figures of Merit (FOM), making it promising for realworld authentication scenarios. Its outstanding trade-off between performance and practicality positions it as a compelling solution for secure applications, including Internet of Things (IoT) devices and other security-critical systems.

This paper presents design details and measurement results of LArASIC, a front-end application specific integrated circuit (ASIC) designed for low-noise readout of charge signals generated in neutrino study experiments within liquid argon time projection chambers. LArASIC comprises of 16-channels of programmable charge amplification and pulse shaping stages that provide a voltage readout proportional to the input charge and was optimized for operation at liquid argon temperature, i.e., 89 K. The chip was fabricated in a 180 nm CMOS process. Measurements at liquid nitrogen temperature, i.e., 77 K, indicate that the channel outputs have high linearity (INL < 0.1%) within the operating range, an equivalent noise charge of 534 electrons for a peaking time of 1µs and a detector capacitance of 150 pF, and a worst-case inter-channel cross-talk of 0.35%. The paper also presents design choices made in the process of migrating LArASIC to CHARMS, an ASIC to be fabricated in a 65 nm process that includes all features provided by LArASIC, along with additional digital programmability for improved robustness and flexibility. CHARMS is intended for use in future high-energy physics experiments that require high-resolution charge or light readout with shorter pulse peaking times.

Transistor sizing and spacing are constantly decreasing due to the continuous advancement of CMOS technology. The charge of the sensitive nodes in the static random access memory (SRAM) cell gradually decreases, making the SRAM cell more and more sensitive to soft errors, such as single-node upsets (SNUs) and double-node upsets (DNUs). Therefore, two types of radiation-hardened SRAM cells are proposed in this article. First, a low-power DNU self-recovery S6P8N cell is proposed. This cell can realize SNU self-recovery from all sensitive nodes as well as realize partial DNU self-recovery and has low-power consumption overhead. Second, we propose a high-speed DNU self-recovery S8P6N cell, which has a soft-error tolerance equivalent to the S6P8N. Furthermore, it reduces the read access time (RAT) and write access time (WAT). Simulation results show that the proposed cells are self-recovery for all SNUs and most of DNUs. Compared with RHBD12, QC8M2T, QC8CE12T, RHM10T, SEA14T, RHM-12T, S8P4R, S8P8M, RH-14T, HRLP16T, GC16T, and HRH-12T, the average power consumption of S6P8N is reduced by 48.78%, and the average power consumption of S8P6N is reduced by 26.34%. At the same time, WAT and RAT are reduced by 9.07% and 36.84%, respectively.

Automotive Ethernet is considered to be the backbone of future in-vehicle data communication. One main feature is its ability to simultaneously transmit data and energy via power over data lines (PoDL). This article proposes the design of a single-ended high-voltage (HV)-compliant 11-bit current-steering digital-to-analog converter (DAC). The converter is tailored for the utilization as digitally controlled current source in adaptive noise-cancellation filter for PoDL networks. Designed in an HV-compliant 180-nm bipolar complementary metal-oxide-semiconductor (BiCMOS) semiconductor technology, the DAC features a monolithically combined topology of two identical 10-bit low-voltage (LV) current-steering DACs supplied at 1.8 V and two complementary HV-compliant output current stages. Main design features of the segmented LV DAC are the utilization of single-ended current cells with an optimized switching logic, proposed to enhance the cells inherent performance and energy efficiency. Furthermore, a newly derived 0.4° asymmetric output walk switching scheme is investigated. At a maximum output voltage swing of 6 V, the proposed DAC provides a bidirectional output current with the amplitude of up to 50 mA. The proposed DAC exhibits the highest voltage compliance combined with large output current capability reported to date for HV-DACs. It also features excellent dynamic performance with a spurious free dynamic range (SFDR) of 57.8 dB as well as measured four sample rates enabling up to 1.6 MS/s and a maximum integral nonlinearity (INL) error of 1.61 LSB and a differential nonlinearity (DNL) error of 1.05 LSB.

In this work, we present our control variate approximation technique that enables the exploitation of highly approximate multipliers in Deep Neural Network (DNN) accelerators. Our approach does not require retraining and significantly decreases the induced error due to approximate multiplications, improving power efficiency and accuracy. As a result, control variate approximation enables satisfying tight error resilience requirements while preserving the power savings. Our experimental evaluation, across six different DNNs and several approximate multiplier designs, demonstrates the versatility of control variate technique and shows that compared to the accurate designs, it achieves the same performance, 45% power reduction, and less than 1% average accuracy loss. Compared to the corresponding approximate designs without using our technique, the error-correction of the control variate method improves the accuracy by 1.9x on average.

This letter presents a novel hardware-efficient approximate 4-2 compressor design that significantly enhances accuracy through a systematic analysis of input patterns obtained from practical applications. We incorporate a majority operation and a compound gate in the compressor design to effectively boost hardware efficiency in multiplication. Our design approach results in substantial error reductions, with normalized mean error distance (NMED) and mean relative error distance (MRED) decreasing by up to 74.84% and 82.04%, respectively, compared to existing approximate multipliers discussed in this letter. When implemented in a 32-nm CMOS technology, the approximate multiplier adopting the proposed 4-2 compressor achieves excellent hardware efficiency, reducing area, power, and energy consumption by up to 8.95%, 13.02%, and 13.02%, respectively, compared to other alternatives. Moreover, our design delivers enhanced performance in image processing, achieving up to a 4.84× increase in peak signal-to-noise ratio (PSNR) compared to other designs, all while optimizing hardware efficiency.

This article presents a new and novel nonoverlapping clock (NOC) generator based on a laddered inverter (LI) circuit. Unlike conventional approaches, the proposed NOC combines the clock generation and pulsewidth-modulation (PWM) circuit into one integrated architecture, offering lower power consumption, smaller area, and a more robust solution. Furthermore, the proposed NOC offers an inherent guarantee of the nonoverlap (dead time) between the output signals thanks to the guaranteed monotonicity of the LI circuit, thus offering a layout-agnostic design. The proposed NOC can also offer dead-time reconfigurability with the help of multiplexers, allowing both calibration and fine-tuning of the dead times to meet specific requirements. We provide a comprehensive assessment of the proposed NOC through simulation and measurement results in 65-nm CMOS. Measured results show that the proposed NOC consumes 1 µW at 5 MHz with a 1-V supply, achieving more than 10× lower power consumption and 25% smaller area compared to the conventional clock circuit. The proposed NOC demonstrates the capability to generate waveforms with frequencies up to 3.5 GHz at a 1.2-V supply, as validated through simulations.

AIn this article, an area-efficient VLSI architecture scheme for high-throughput computation of the 2-D discrete wavelet transform (DWT) is proposed, effectively applied in the context of aircraft cargo hold scenes. The proposed architecture aims to reduce computation and storage resources while maintaining the DWT-IDWT reconstructed image quality for the 9/7 discrete wavelet. The hardware implementation formulae based on the flipping architecture have been modified to reduce RAM storage bit width. By transforming the coefficients of the formula into hardware-friendly values, the required multiplication operations are split into two stages of addition. On this basis, a pipelined architecture is constructed to set the critical path delay (CPD) of the architecture to be close to the delay of a single adder, Tₐ, thereby achieving a high throughput. Compared to existing architectures in the research field, the proposed single-level 2-D DWT architecture achieves resource savings on the field-programmable gate array (FPGA) platform while ensuring good image reconstruction quality. The advantages of the multilevel 2-D DWT are evaluated, and the results show similar results on the application-specific integrated circuit (ASIC) platform. The proposed architecture reduces average computation time by at least 35.54% while achieving delay of one-level decomposition, decreases the area-delay product (ADP) by at least 25.41%, and saves a significant amount of energy per image (EPI). Furthermore, the proposed folded architecture achieves close to 100% hardware utilization efficiency (HUE) in multilevel 2-D DWT computations.

This article presents the conception, design, and realization of a fully differential two-stage CMOS amplifier that is unconditionally stable for any value of the capacitive load. This is simply achieved by sending a scaled replica of the output stage current to the amplifier virtual ground in order to create a left half-plane (LHP) zero in the loop gain that either cancels or tracks the output pole in all process, voltage, and temperature (PVT) conditions. Consequently, from a stability point of view, the amplifier behavior resembles that of a single-pole OTA. Starting from an existing two-stage gain-programmable amplifier, designed in a 0.18-µm bipolar-CMOS-DMOS (BCD) process that was able to drive only 10 pF without encountering into stability issues, a simple circuit has been added to extend the stability to any capacitive load value. An interesting and unusual method, based on the frequency behavior of the unloaded closed-loop amplifier output impedance, has been introduced to further verify the unconditional stability of this solution. Measurements show a high degree of stability in any load conditions. In the used 0.18-µm BCD technology, silicon area and current consumption of the extra circuit are only 0.0004 mm² and 2 µA, respectively, with a 5-V power supply.

Three-dimensional NAND flash memory using the advanced multibit-per-cell technique is widely adopted due to its high density. However, it faces the problem of deteriorating read performance and energy consumption due to decreased reliability. Low-density parity-check code (LDPC) is typically adopted as an error correction code (ECC) to encode data and provide fault tolerance. To reduce the cost, LDPC with a high code rate is always adopted. However, LDPC will lead to read retry operations when the accessed data are not successfully decoded, and such retry-induced performance degradation is serious, especially for modern high-density flash memory. In this work, a reliability-aware differential ECC (READECC) approach is proposed to reduce redundancy protection and storage cost of LDPC with a low cost. The basic idea is to adopt LDPC with a suitable code rate considering both data access characteristics and flash reliability characteristics. First, hot reads are strengthened based on the frequency of being accessed. Second, based on the reliability variation characteristics, the life of NAND flash is divided into three reliability periods. As the reliability period shifts, the code rate of the LDPC adjusts adaptively to minimize redundancy overhead. Furthermore, the READECC scheme provides further flexibility to support LDPC with strong error correction capability only when paired with a low redundancy rate. With careful design and evaluation on 3-D triple-level cell NAND flash memory, READECC achieves encouraging optimizations with a negligible cost.

A follower-based gₘ – C low-pass filter that employs CMOS vertical source-couple-pair (VSCP) transconductors is proposed for practical use in EEG acquisition systems. The VSCP transconductor operates as a gₘ cell with current sharing and linearity enhancement features. It is featured in the first- and second-order gₘ – C sections cascaded to form a third-order low-pass filter targeting a 150-Hz bandwidth. To mitigate the effects of biasing current source mismatch, dynamic element matching (DEM) is optionally applied to the relevant biasing current source pairs, resulting in second harmonic distortion (HD2) and noise suppression. Implemented in a 0.18-µm process, the proposed filter consumes 16.3-nW power from a 1.2-V supply. Thanks to the DEM and VSCPS, the linear bandwidth is 150-Hz with linear input range (measured at 1% total harmonic distortion (THD)), whereas the dynamic range for less than 4 µV₍rms₎ noise is obtained to a filter dynamic range (DR) of 65.15 dB. Overall performance comparisons with other recent biomedical filters indicate that the figure of merit (FoM) of this proposed filter is comparable while the linear input range is larger.

A multiply-accumulator, often abbreviated as a MAC unit, is central to a multitude of computational tasks, particularly those tasks (such as neural networks) involving array-based mathematical computations. The quest for novel methods to efficiently store and process data in a MAC has become imperative. Recently, ternary logic has attracted significant attention due to its higher information density than conventional binary systems. However, though numerous studies have showcased ternary arithmetic techniques, advancements in ternary-based vector processing have been notably scarce. To bridge this gap, this work undertakes comprehensive study into the optimization of ternary MAC units. Firstly, we propose various ternary approximate algorithms, which allow 30% less power consumption and 21% compact area in comparison with the accurate design. Secondly, we design sophisticated ternary circuits and obtain 74%–86% lower power-delay-product (PDP) than previous works. Furthermore, we evaluate proposed ternary MAC unit using both carbon-nanotube field-effect transistor (CNFET) and silicon-based 180 nm CMOS processes. The simulation results show the ternary circuit is better than binary circuit in terms of both area (~45% less) and power (~30% less), highlighting its strong potential for practical applications.

Advanced Internet-of-Things (IoT) devices are increasingly used in high-temperature environments, such as automotive, aerospace, defense, and industrial applications. High-temperature voltage references are crucial for these systems. This paper presents two topologies designed for high-temperature operation. The first topology minimizes leakage currents by using a replica branch to decouple leakage from the core, reducing its impact on the reference voltage. The second topology optimizes the operating temperature by employing one-stage amplifiers as buffers to handle junction leakage while maintaining body voltage. Both designs are fabricated in 180 nm CMOS process. The first design supports operation up to 140 °C with an average temperature coefficient (TC) of 70 ppm/°C, while the second design operates up to 180 °C with a TC of 64 ppm/°C. The designs also exhibit line sensitivities of 0.46 %/V and 0.31 %/V, PSRRs of –37.8 dB and –38.8 dB at 100 Hz, and power consumption of 111 pW and 136.8 pW at room temperature, respectively.

In this paper we propose a novel approximate floating-point divider based on bidimensional linear approximation. In our approach, the mantissa quotient is seen as a function of the two input mantissas of the divider. The domain of this two-variable function is partitioned into nx × ny subregions, named tiles, where nx, ny are chosen as powers of two. In each tile the quotient is approximated with a linear combination of the input mantissas. To achieve fine accuracy, an optimization problem is formulated within each tile to determine the optimal coefficients for the linear combination, which minimize the Mean Relative Error Distance (MRED) of the divider. Furthermore, to make hardware implementation more effective, the minimization problem is appropriately modified to search for optimal quantized coefficients. The hardware structure of the divider only requires a small look-up table to store the linear approximation coefficients, and a carry save adder tree. The proposed architecture is highly tunable at design-time over a wide range of accuracy, depending on the number of tiles chosen for the approximation. The obtained results demonstrate error performance and hardware features superior to the state-of-the-art. The proposed dividers define the Pareto front, considering the trade-off between power-delay-product vs. MRED and area-delay-product vs. MRED, for MRED in the range of 4 × 10−3 − 2 × 10−2 . Application results for JPEG compression and tone mapping further highlight the strength of our proposal, which exhibits Structural Similarity Index (SSIM) very close to 1 in all cases and Peak Signal-to-Noise Ratio (PSNR) up to 45 dB.

Soft errors in Integrated Circuits (ICs) have always been a major concern, particularly as CMOS technology nodes continue to shrink, resulting in higher frequency, lower power, and smaller areas, exacerbating radiation-induced soft errors. Therefore, Single Event Transient (SET) has become a crucial consideration in designing modern radiation-tolerant circuits, as it has the potential to cause failures in circuit outputs. This paper employs the concept of signal probability for transient fault propagation in circuits. Considering the issue of transient fault-masking, an error propagation model is presented for each fault-masking case. Furthermore, approaches are proposed for both probabilistic and time-based scenarios to address the impact of re-convergent paths on transient faults. Since considering re-convergent paths increases computational complexity, three computational approximations are proposed in this paper as a compromise to reduce the size of simulation runs as much as possible. We compared the simulation results with Monte-Carlo methods and HSPICE-based simulations to validate the proposed method. According to the comparison results on ISCAS-85 benchmarks, the proposed approach for estimating the SER exhibits an average accuracy of 95% while consuming less than 5% compared to traditional fault injection.