VLSI IEEE Projects 2015-2016
VLSI IEEE Projects 2015-2016
Vlsi IEEE Projects 2015-2016 We are offering ieee projects 2015-2016 in latest technology like Java, dot net, android, embedded, matlab, vlsi, hadoop, power elctronics, power system, mechanical, civil projects. IEEE Master is a unit of LeMeniz Technologies. We guide all final year M.E/M.Tech, B.E/B.Tech, MPhil, MCA, BCA, M.Sc, B.Sc, and Diploma students for their Academic Projects to get best results.
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IEEE Project Technology
- Java
- Dotnet
- Android
- Hadoop
- NS2
- Matlab
- Embedded
- VLSI
- Power System
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- Mechanical
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VLSI IEEE Projects Titles
| S.NO | Code | Title | Year |
|---|---|---|---|
| S.NO | Code | Title | Year |
| 1 | LM_VL015_01 | A Low-Cost Low-Power All-Digital Spread-Spectrum Clock Generator | 2015 |
| 2 | LM_VL015_02 | A Combined SDC-SDF Architecture for Normal I/O Pipelined Radix-2 FFT | 2015 |
| 3 | LM_VL015_03 | A Class of SEC-DEDDAEC Codes Derived From Orthogonal Latin Square Codes | 2015 |
| 4 | LM_VL015_04 | Design of Efficient Content Addressable Memories in High-Performance FinFET Technology | 2015 |
| 5 | LM_VL015_05 | A New Efficiency-Improvement Low-Ripple Charge-Pump Boost Converter Using Adaptive Slope Generator With Hysteresis Voltage Comparison Techniques | 2015 |
| 6 | LM_VL015_06 | A 0.25-V 28-nW 58-dB Dynamic Range Asynchronous Delta Sigma Modulator in 130-nm Digital CMOS Process | 2015 |
| 7 | LM_VL015_07 | Range Unlimited Delay-Interleaving and -Recycling Clock Skew Compensation and Duty-Cycle Correction Circuit | 2015 |
| 8 | LM_VL015_08 | Obfuscating DSP Circuits via High-Level Transformations | 2015 |
| 9 | LM_VL015_09 | Accelerating Scalar Conversion for Koblitz Curve Cryptoprocessors on Hardware Platforms | 2015 |
| 10 | LM_VL015_10 | Design of Self-Timed Reconfigurable Controllers for Parallel Synchronization via Wagging | 2015 |
| 11 | LM_VL015_11 | Level-Converting Retention Flip-Flop for Reducing Standby Power in ZigBee SoCs | 2015 |
| 12 | LM_VL015_12 | All Digital Energy Sensing for Minimum Energy Tracking | 2015 |
| 13 | LM_VL015_13 | Recursive Approach to the Design of a Parallel Self-Timed Adder | 2015 |
| 14 | LM_VL015_14 | Novel Reconfigurable Hardware Architecture for Polynomial Matrix Multiplications | 2015 |
| 15 | LM_VL015_15 | Implementation of Subthreshold Adiabatic Logic for Ultralow-Power Application | 2015 |
| 16 | LM_VL015_16 | FPGA-Based Bit Error Rate Performance Measurement of Wireless Systems | 2015 |
| 17 | LM_VL015_17 | Algorithm and Architecture Design of the H.265/HEVC Intra Encoder | 2015 |
| 18 | LM_VL015_18 | Pre-Encoded Multipliers Based on Non-Redundant Radix-4 Signed-Digit Encoding | 2015 |
| 19 | LM_VL015_19 | A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications | 2015 |
| 20 | LM_VL015_20 | A Novel Photosensitive Tunneling Transistor for Near-Infrared Sensing Applications: Design, Modeling, and Simulation | 2015 |
| 21 | LM_VL015_21 | High-Throughput LDPCDecoder Architecture Using Efficient Comparison Techniques & Dynamic Multi-Frame Processing Schedule | 2015 |
| 22 | LM_VL015_22 | A New Parallel VLSI Architecture for Real-time Electrical Capacitance Tomography | 2015 |
| 23 | LM_VL015_23 | Graph-Based Transistor Network Generation Method for Supergate Design | 2015 |
| 24 | LM_VL015_24 | A Relative Imaging CMOS Image Sensor for High Dynamic Range and High Frame-Rate Machine Vision Imaging Applications | 2015 |
| 25 | LM_VL015_25 | Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication | 2015 |
| 26 | LM_VL015_26 | Fully Pipelined Low-Cost and High-Quality Color Demosaicking VLSI Design for Real-Time Video Applications | 2015 |
| 27 | LM_VL015_27 | A Novel Area-Efficient VLSI Architecture for Recursion Computation in LTE Turbo Decoders | 2015 |
| 28 | LM_VL015_28 | Comparative Performance Analysis of the Dielectrically Modulated FullGate and Short-Gate Tunnel FET-Based Biosensors | 2015 |
| 29 | LM_VL015_29 | An Efficient Constant Multiplier Architecture Based on Vertical- Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis | 2015 |
| 30 | LM_VL015_30 | VLSI-Assisted Nonrigid Registration Using Modified Demons Algorithm | 2015 |
| 31 | LM_VL015_31 | Fine-Grained Access Management in Reconfigurable Scan Networks | 2015 |
| 32 | LM_VL015_32 | A High-Throughput VLSI Architecture for Hard and Soft SC-FDMA MIMO Detectors | 2015 |
| 33 | LM_VL015_33 | Partially Parallel Encoder Architecture for Long Polar Codes | 2015 |
| 34 | LM_VL015_34 | Novel Block-Formulation and Area-Delay-Efficient Reconfigurable Interpolation Filter Architecture for Multi-Standard SDR Applications | 2015 |
| 35 | LM_VL015_35 | One Minimum Only Trellis Decoder for Non-Binary Low-Density Parity-Check Codes | 2015 |
| 36 | LM_VL015_36 | A Low-Cost Hardware Architecture for Illumination Adjustment in Real-Time Applications | 2015 |
| 37 | LM_VL015_37 | A 2.5-Gb/s DLL-Based Burst-Mode Clock and Data Recovery Circuit With 4× Oversampling | 2015 |
| 38 | LM_VL015_38 | Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic | 2015 |
| 39 | LM_VL015_39 | Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations | 2015 |
| 40 | LM_VL015_40 | Fully Reused VLSI Architecture of FM0/Manchester Encoding Using SOLS Technique for DSRC Applications | 2015 |
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