IEEE Transactions on VLSI 2026 Research Papers
IEEE Transactions on VLSI 2026 Research Papers
IEEE Transactions on VLSI 2026 Research Papers, We are offering iee projects 2025-2026 in latest technology like Java, dot net, android, embedded, matlab, vlsi, hadoop, power elctronics, power system, mechanical, civil projects. IEEE Master is a unit of LeMeniz Technologies. We guide all final year M.E/M.Tech, B.E/B.Tech, MPhil, MCA, BCA, M.Sc, B.Sc, and Diploma students for their Academic Projects to get best results.
Why Us?
- 24 X 7 Online Supports
- No False Commitment
- Affordable Price
- On Time Project Delivery
- Project Execution on student laptop
- Project Completion Certificate
- Output Video
- Project Requirement Specification
- Software Requirement Specification
- Project Flow Diagram
- Project Documentation
- Working Source Code
- PPT
IEEE Project Technology
- Java
- Dotnet
- Android
- Hadoop
- NS2
- Matlab
- Embedded
- VLSI
- Power System
- Power Electronics
- Mechanical
- Civil
LOW POWER
LOW POWER VLSI IEEE TRANSACTION PROJECTS 2026
| S.No | Code | Title | Year |
|---|---|---|---|
| 1 | VLSI_2026_03 | DBP-CIM: Energy-Efficient 8T SRAM-Based Diagonal-Block Parallel Computing-in-Memory | 2026 |
| 2 | VLSI_2026_04 | A 9T SRAM Computation-in-Memory Architecture With High-Precision MAC | 2026 |
| 3 | VLSI_2026_05 | A 25-Mb/s 4-ASK Receiver Front-End in 65-nm CMOS | 2026 |
| 4 | VLSI_2026_10 | Design Criteria for 4-Stage Pseudo-Differential Ring Oscillators | 2026 |
| 5 | VLSI_2026_12 | An Area-Efficient Fractional Output Divider | 2026 |
| 6 | VLSI_2026_13 | A 6-GS/s 8-bit Time-Domain ADC | 2026 |
| 7 | VLSI_2026_14 | Frequency Synchronization Techniques for DC–DC Converters | 2026 |
| 8 | VLSI_2026_15 | A 109-dB SFDR Continuous-Time Delta-Sigma Modulator | 2026 |
| 9 | VLSI_2026_16 | A Compact and Efficient 40 V Capacitive Level Shifter | 2026 |
| 10 | VLSI_2026_18 | A Reconfigurable Built-In Self-Test Scheme | 2026 |
| 11 | VLSI_2026_20 | A 40-nm Embedded Flash | 2026 |
| 12 | VLSI_2026_22 | A Fully Integrated Storage-Free Energy Harvesting System | 2026 |
| 13 | VLSI_2026_31 | A Tri-Band Two-Stage LNA for WiFi | 2026 |
| 14 | VLSI_2026_32 | A 0.31-V 16-Kb 9T SRAM | 2026 |
| 15 | VLSI_2026_33 | FADE: Fault-Aware Adaptive On-Die ECC | 2026 |
| 16 | VLSI_2026_34 | A Pattern-Dependent Pulse Filtering Technique | 2026 |
| 17 | VLSI_2026_35 | A Low-Cost Dual-Mode ASK Demodulator IoT Tag | 2026 |
| 18 | VLSI_2026_36 | Phase and Amplitude Imbalances in Quadrature LC CMOS Oscillators | 2026 |
| 19 | VLSI_2026_37 | A Complementary 3T-Based eDRAM Macro | 2026 |
| 20 | VLSI_2026_38 | Design for Slew-Rate in Multi-Stage CMOS OTAs | 2026 |
| 21 | VLSI_2026_46 | A 1.5-GS/s 7-bit Charge-Injection SAR ADC | 2026 |
| 22 | VLSI_2026_49 | An 8-bit Precision 10T SRAM Compute-in-Memory Macro | 2026 |
| 23 | VLSI_2026_67 | Energy-Efficient Izhikevich Neuron Design | 2026 |
| 24 | VLSI_2026_69 | A Counter-Based Addition Circuit Design | 2026 |
| 25 | VLSI_2026_70 | An Approximate Digital CIM Macro | 2026 |
| 26 | VLSI_2026_74 | High-Speed Floating Voltage Level Shifter | 2026 |
| 27 | VLSI_2026_75 | A T8T-SRAM Computing-in-Memory Macro | 2026 |
| 28 | VLSI_2026_77 | Multioutput SAR SC DC-DC Converter | 2026 |
| 29 | VLSI_2026_78 | 1.3 TFLOPS/mm² Floating-Point SRAM-Based CIM Macro | 2026 |
| 30 | VLSI_2026_79 | 40 nm Buffer-Free 7T-SRAM Analog Charge-Domain CIM Macro | 2026 |
| 31 | VLSI_2026_83 | A Low Area Built-In Self-Repair for HBM | 2026 |
AREA EFFICIENT/ TIMING & DELAY REDUCTION
VLSI IEEE TRANSACTION AE PROJECTS 2026
| S.No | Code | Title | Year |
|---|---|---|---|
| 1 | VLSI_2026_06_AE | VASE: Vector Memory Using Bit-Level Address Segmentation for High-Speed Memory Testing | 2026 |
| 2 | VLSI_2026_08_AE | DiP: A Scalable, Energy-Efficient Systolic Array for Matrix Multiplication Acceleration | 2026 |
| 3 | VLSI_2026_09_AE | Pipe-LPAQ: A Fully Pipelined Architecture for LPAQ Data Compression on FPGA | 2026 |
| 4 | VLSI_2026_17_AE | Countering Side-Channel Attacks With a Dynamic S-Box Based on Affine Transformations | 2026 |
| 5 | VLSI_2026_19_AE | High Throughput and Compact FPGA TRNGs Based on Hybrid Entropy | 2026 |
| 6 | VLSI_2026_24_AE | EVMx: An FPGA-Based Accelerator for Smart Contract Processing | 2026 |
| 7 | VLSI_2026_25_AE | Unified FPGA Accelerator for Elliptic-Curve-Based Functions | 2026 |
| 8 | VLSI_2026_26_AE | Exa: Unified Architecture for Multi-Scalar Multiplication | 2026 |
| 9 | VLSI_2026_27_AE | A RISC-V Accelerator for Sequence Decoding in Mobile DNA Sequencers | 2026 |
| 10 | VLSI_2026_29_AE | Area-Time Efficient Formula-Based BCH Decoder | 2026 |
| 11 | VLSI_2026_30_AE | An LSGQ-FFS Framework for Adaptive Optimization | 2026 |
| 12 | VLSI_2026_40_AE | Construction of Lightweight S-Boxes With Low Boomerang Uniformity | 2026 |
| 13 | VLSI_2026_41_AE | Modular, Low-Cost Bus and ECC Encoders | 2026 |
| 14 | VLSI_2026_42_AE | Scalable Segment-Parallel Architecture for Lossless Data Compression | 2026 |
| 15 | VLSI_2026_44_AE | High-Speed FPGA Implementation for IVF-PQ Index Construction | 2026 |
| 16 | VLSI_2026_45_AE | TRIM: Acceleration of Multiplication-Less Neural Networks | 2026 |
| 17 | VLSI_2026_47_AE | Seamless Mode Transition Scheme With DCM Compensation | 2026 |
| 18 | VLSI_2026_51_AE | A Counter-Based Addition Circuit Design for Stochastic Computing | 2026 |
| 19 | VLSI_2026_53_AE | Hierarchical Approximate Min-Sum QC-LDPC Decoder | 2026 |
| 20 | VLSI_2026_55_AE | FPGA-Based High-Speed Gray-Code Phase Shift Profilometry System | 2026 |
| 21 | VLSI_2026_59_AE | Resource Reuse Strategy for Large-Scale Matrix Operations | 2026 |
| 22 | VLSI_2026_64_AE | Two Novel Approximate Radix-4 Booth Encoders | 2026 |
| 23 | VLSI_2026_66_AE | Efficient Approximate Ternary Multipliers for Nanodevices | 2026 |
| 24 | VLSI_2026_68_AE | Efficient Logarithmic Converter Circuit Design | 2026 |
| 25 | VLSI_2026_71_AE | Big Integer Parallel Stream Modular Multiplier | 2026 |
| 26 | VLSI_2026_72_AE | Fusing Adds and Shifts for Efficient Dot Products | 2026 |
| 27 | VLSI_2026_73_AE | HFMLLR: Heterogeneous Feature Mining for LDPC Codes | 2026 |
| 28 | VLSI_2026_81_AE | Area-Efficient and Reconfigurable Accelerator for Massive MIMO | 2026 |
| 29 | VLSI_2026_84_AE | FPGA-Based Low-Power Signed Approximate Multipliers | 2026 |
| 30 | VLSI_2026_85_AE | Delay-Element-Based Technique for Enhancing Soft Error Tolerance | 2026 |
| 31 | VLSI_2026_86_AE | Entropy Model of FIRO-Based TRNGs With Differential Structure | 2026 |
| 32 | VLSI_2026_87_AE | Efficient Approximate Radix-8 Booth Multiplier for Edge Detection | 2026 |
| 33 | VLSI_2026_89_AE | Efficient Multiplierless FPGA Architecture for Rulkov Neuron Mapping | 2026 |
| 34 | VLSI_2026_90_AE | A Phase-Walk-Based True Random Number Generator | 2026 |
HIGH SPEED DATA TRANSMISSION & Networking
VLSI IEEE TRANSACTION HS PROJECTS 2026
| S.No | Code | Title | Year |
|---|---|---|---|
| 1 | VLSI_2026_01_HS | FPGA-Based Real-Time ECG Classification System Using Quantized Inception-ResNeXt Neural Network and CWT Approximation | 2026 |
| 2 | VLSI_2026_28_HS | An Efficient VLSI Architecture for Hammerstein-Type Spline Adaptive Filters | 2026 |
| 3 | VLSI_2026_39_HS | A High-Energy-Efficiency Lightweight BNN Accelerator for Arrhythmia Detection | 2026 |
| 4 | VLSI_2026_48_HS | An Area-Efficient Normal Input/Output Ordered Memory-Based FFT Using an SC Kernel | 2026 |
| 5 | VLSI_2026_50_HS | An IR-UWB Transmitter Using Two-Dimensional Differential Pulse Position Modulation | 2026 |
| 6 | VLSI_2026_52_HS | FPGA Implementation of a Real-Time Parallel Loop-Unrolled DFE for PAM-4 IM/DD Optical Links | 2026 |
| 7 | VLSI_2026_54_HS | EVMx: An FPGA-Based Accelerator for Smart Contract Processing | 2026 |
| 8 | VLSI_2026_56_HS | A 32-Channel, Low Resources and High-Precision FPGA Time-to-Digital Converter (TDC) | 2026 |
| 9 | VLSI_2026_61_HS | Scalable Network-on-Chip Design for FPGA Implementation | 2026 |
| 10 | VLSI_2026_62_HS | Single-Stage Flip PAM-8 Signal Transmission for W-Band Wireless System | 2026 |
| 11 | VLSI_2026_65_HS | Analytical Error Evaluation and Hardware Implementation of Approximate Negation Circuits | 2026 |
| 12 | VLSI_2026_76_HS | Hardware-Accelerated ASIC and Cardiac Monitoring System for Wearable Devices | 2026 |
| 13 | VLSI_2026_80_HS | HSA: An Efficient Sparse CNN Accelerator Based on Kernel-Aware Hybrid Pruning | 2026 |
| 14 | VLSI_2026_82_HS | A 48-Gb/s PAM-4 Transceiver With Transition Boosting and RLM Calibration | 2026 |
| 15 | VLSI_2026_88_HS | Noise Modulation of a Bandgap Reference by Using a Single Resistor | 2026 |
VLSI Design of Image, Video and Audio Processing
VLSI IEEE TRANSACTION AE PROJECTS 2026
| S.No | Code | Title | Year |
|---|---|---|---|
| 1 | VLSI_2026_02_IM | An Efficient Accelerator for Dehazing Neural Network Based on Physical Perception Model and Cross-Scale Pixel Attention | 2026 |
| 2 | VLSI_2026_07_IM | EDCSSM: Edge Detection With Convolutional State Space Model | 2026 |
| 3 | VLSI_2026_11_IM | Event-Triggered Multi-Kernel Learning-Based Stochastic MPC With Applications in Building Climate Control | 2026 |
| 4 | VLSI_2026_21_IM | An Energy-Efficient Kalman Filter Coprocessor Design for Multiple-Object Tracking | 2026 |
| 5 | VLSI_2026_23_IM | AHCO-YOLO: An Algorithm–Hardware Co-Optimization Framework for Real-Time Object Detection | 2026 |
| 6 | VLSI_2026_43_IM | TEA-SPS: A Tiny and Efficient Architecture for Softmax With Parallelism and Sparsity Adaptability | 2026 |
| 7 | VLSI_2026_58_IM | Pipe-LPAQ: A Fully Pipelined Architecture for LPAQ Data Compression on FPGA | 2026 |
| 8 | VLSI_2026_60_IM | FPGA-Based Medical Image Processing Using Hardware-Software Co-Design Approach | 2026 |
| 9 | VLSI_2026_63_IM | Power Efficient Multiplier Design for Error Resilient Edge Applications | 2026 |
+91 9566475911 | +91 9962588976 | projects@lemenizinfotech.com