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IEEE MASTER – IEEE PROJECTS IN PONDICHERRY
VLSI IEEE Projects 2016-2017, VLSI IEEE Projects Titles 2016-2017 We are offering ieee projects 2016-2017 in latest technology like Java ieee projects, dotnet ieee projects, android ieee projects, embedded ieee projects, matlab ieee projects, Digital Image Processing ieee projects, vlsi ieee projects, hadoop ieee projects, power electronics ieee projects, power system ieee projects, mechanical ieee projects, civil ieee projects. IEEE Master is a unit of LeMeniz Technologies. We guide all final year M.E/M.Tech, B.E/B.Tech, MPhil, MCA, BCA, M.Sc, B.Sc, and Diploma students for their Academic Projects to get best results.
| S.No | Code | IEEE Based on Low Power | Year |
|---|---|---|---|
| A Fully Digital Front-End Architecture for ECG Acquisition System with 0.5v Supply | |||
| Low-Cost High Performance VLSI Architecture for Montgomery Modular Multiplication | |||
| RF Power Gating: A Low-Power Technique for Adaptive Radios | |||
| A New Parallel VLSI Architecture for Real-Time Electrical Capacitance Tomography | |||
| Low-Power FPGA Design Using Memoization-Based Approximate Computing | |||
| Low-Power Split-Radix FFT Processors Using Radix-2 Butterfly Units | |||
| A 3-D CPU-FPGA_DRAM Hybrid architecture for Low-Power Computation | |||
| Design of a Network of Digital Sensor Macros for Extracting Power Supply Noise Profile in SoCs | |||
| The Flexible ECC Management for Low-Cost Transient Error Protection of Last-Level Caches |
| S.No | Code | IEEE Based on High Speed Data Transmission | Year |
|---|---|---|---|
| A High-Speed FPGA Implementation of an RSD-Based ECC Processor | |||
| High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels | |||
| A 0.52/1 V Fast Lock-in ADPLL for Supporting Dynamic Voltage and Frequency Scaling | |||
| Code Compression for Embedded Systems Using Separated Dictionaries | |||
| A Dynamically Reconfigurable Multi-ASIP Architecture for Multistandard and Multimode Turbo Decoding | |||
| Design and Implementation of High-Speed All-Pass Transformation- Based Variable Digital Filters by Breaking the Dependence of Operating Frequency on Filter Order | |||
| Statistical Framework and Built-In Self Speed-Binning System for Speed Binning Using On-Chip Ring Oscillators | |||
| A Low-Power Broad-Bandwidth Noise Cancellation VLSI Circuit Design for In-Ear Headphones | |||
| Source Coding and Preemphasis for Double-Edged Pulse width Modulation Serial Communication | |||
| A Fast-Acquisition All-Digital Delay-Locked Loop Using a Starting-Bit Prediction Algorithm for the Successive-Approximation Register | |||
| GPU-Accelerated Parallel Sparse LU Factorization Method for Fast Circuit Analysis | |||
| An All-Digital Approach to Supply Noise Cancellation in Digital Phase- Locked Loop | |||
| Design of Modified Second-Order Frequency Transformations Based Variable Digital Filters With Large Cutoff Frequency Range and Improved Transition Band Characteristics |
| S.No | Code | IEEE Based on Networking | Year |
|---|---|---|---|
| In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers | |||
| FCUDA-NoC : A Scalable and Efficient Network-on-Chip Implementation for the CUDA-to-FPGA Flow | |||
| Process Variation Delay and Congestion Aware Routing Algorithm for Asynchronous NoC Design | |||
| Argo: A Real-Time Network-on-Chip Architecture With an Efficient GALS Implementation | |||
| Efficient Dynamic Virtual Channel Organization and Architecture for NoC Systems | |||
| A New CDMA Encoding/Decoding Method for on-Chip Communication Network |
| S.No | Code | IEEE Based on Audio, Image & Video Processing | Year |
|---|---|---|---|
| Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding | |||
| A Configurable Parallel Hardware Architecture for Efficient Integral Histogram Image Computing | |||
| A New Binary-Halved Clustering Method and ERT Processor for ASSR System | |||
| The VLSI Architecture of a Highly Efficient De-blocking Filter for HEVC Systems |
| S.No | Code | IEEE Based on Tanner & Microwind/DSCH3 | Year |
|---|---|---|---|
| A Single-Ended With Dynamic Feedback Control 8T Subthreshold SRAM Cell | |||
| OTA-Based Logarithmic Circuit for Arbitrary Input Signal and Its Application | |||
| A Robust Energy/Area-Efficient Forwarded-Clock Receiver With All- Digital Clock and Data Recovery in 28-nm CMOS for High-Density Interconnects | |||
| Full-Swing Local Bitline SRAM Architecture Based on the 22-nm FinFET Technology for Low-Voltage Operation | |||
| A 0.1–3.5-GHz Duty-Cycle Measurement and Correction Technique in 130-nm CMOS | |||
| A Systematic Design Methodology of Asynchronous SAR ADCs | |||
| Read Bit line Sensing and Fast Local Write-Back Techniques in Hierarchical Bit line Architecture for Ultralow-Voltage SRAMs | |||
| Online Measurement of Degradation Due to Bias Temperature Instability in SRAMs | |||
| Incorporating Process Variations Into SRAM Electromigration Reliability Assessment Using Atomic Flux Divergence | |||
| PROCEED: A Pareto Optimization-Based Circuit-Level Evaluator for Emerging Devices | |||
| A Fast-Transient Wide-Voltage-Range Digital-Controlled Buck Converter With Cycle-Controlled DPWM | |||
| Designing Tunable Subthreshold Logic Circuits Using Adaptive Feedback Equalization | |||
| Dual-Calibration Technique for Improving Static Linearity of Thermometer DACs for I/O | |||
| An Add-On Type Real-Time Jitter Tolerance Enhancer for Digital Communication Receivers | |||
| SRAM-Based Unique Chip Identifier Techniques | |||
| A Low-Power Robust Easily Cascaded PentaMTJ-Based Combinational and Sequential Circuits | |||
| Low-Power Variation-Tolerant Nonvolatile Lookup Table Design | |||
| Low-Energy Power-ON-Reset Circuit for Dual Supply SRAM | |||
| Frequency-Boost Jitter Reduction for Voltage-Controlled Ring Oscillators | |||
| High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for DLL-Based Clock Generator | |||
| EMDBAM: A Low-Power Dual Bit Associative Memory With Match Error and Mask Control | |||
| A Single-Stage Low-Dropout Regulator With a Wide Dynamic Range for Generic Applications | |||
| Power Efficient Level Shifter for 16 nm FinFET Near Threshold Circuits |
VLSI IEEE Projects 2016-2017, VLSI IEEE Projects Titles 2016-2017. We are offering ieee projects 2016-2017 in latest technology like Java ieee projects, dot net ieee projects, android ieee projects, ns2 ieee projects, embedded ieee projects, matlab ieee projects, digital image processing ieee projects, vlsi ieee projects, hadoop ieee projects, power elctronics ieee projects, power system ieee projects, mechanical ieee projects, civil projects ieee project. We guide all final year M.E/M.Tech, B.E/B.Tech, MPhil, MCA, BCA, M.Sc, B.Sc, and Diploma students for their Academic Projects to get best results. We are offering java ieee projects in pondicherry. LeMeniz Infotech is a new class of software concern committed to catalyzing the competence and competitiveness of its clients by helping them succeed through the power of information technology. Driven by the credo that solutions are effective only when organizational needs are accurately ascertained and aptly addressed; LeMeniz Infotech looks upon itself as an integral part of its client’s organization. We have varied and extensive expertise in software development, web portal development, application software development, e-commerce website development, mobile application development, search engine optimization, bulk sms services, social media marketing, ieee projects guidance and more.
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