IEEE Transactions on VLSI 2026 Research Papers
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Project Title
VLSI_2026_03DBP-CIM: Energy-Efficient 8T SRAM-Based Diagonal-Block Parallel Computing-in-Memory With Compact Data Layout for Arithmetic OperationsVLSI_2026_04A 9T SRAM Computation-in-Memory Architecture With High-Precision MAC, Enhanced Bitline Voltage Margin, and Improved Frequency Performance Over Conventional ArchitecturesVLSI_2026_05A 25-Mb/s 4-ASK Receiver Front-End in 65-nm CMOS for Biomedical Data Telemetry via a Capacitive LinkVLSI_2026_10A Study of the Design Criteria for 4-Stage, Pseudo-Differential Ring Oscillators to Self-Start From Any Initial StateVLSI_2026_12An Area-Efficient Fractional Output Divider Based on Foreground DTC INL CalibrationVLSI_2026_13A 6-GS/s 8-bit Time-Domain ADC With Selection-First Pipelined Successive Approximation Register TDC in 28-nm CMOS TechnologyVLSI_2026_14Frequency Synchronization Techniques for DC–DC Converters With Time-Based ControlVLSI_2026_15A 109-dB SFDR Continuous-Time Delta-Sigma Modulator for Audio Using Bi-Directional Advancing Data Weighted AveragingVLSI_2026_16A Compact and Efficient 40 V Capacitive Level Shifter With Feedback Discharge Control for Enhanced CMTI and Low FoM for Bootstrapped Gate Drivers in BCD TechnologyVLSI_2026_18A Reconfigurable Built-In Self-Test Scheme for the Evaluation Circuits of Digital SRAM-IMC Architectures
AREA EFFICIENT / TIMING & DELAY REDUCTION
| Project Code | Project Title |
|---|---|
| VLSI_2026_06_AE | VASE: Vector Memory Using Bit-Level Address Segmentation for High-Speed Memory Testing |
| VLSI_2026_08_AE | DiP: A Scalable, Energy-Efficient Systolic Array for Matrix Multiplication Acceleration |
| VLSI_2026_09_AE | Pipe-LPAQ: A Fully Pipelined Architecture for LPAQ Data Compression on FPGA |
| VLSI_2026_17_AE | Countering Side-Channel Attacks With a Dynamic S-Box Based on Affine Transformations and Gold Sequences |
| VLSI_2026_19_AE | High Throughput and Compact FPGA TRNGs Based on Hybrid Entropy, Reinforcement Strategies, and Automated Exploration |
| VLSI_2026_24_AE | EVMx: An FPGA-Based Accelerator for Smart Contract Processing |
| VLSI_2026_25_AE | Design Space Exploration of a Unified FPGA Accelerator for Elliptic-Curve-Based Functions in Attribute-Based Encryption |
HIGH SPEED DATA TRANSMISSION & NETWORKING
| Project Code | Project Title |
|---|---|
| VLSI_2026_01_HS | FPGA-Based Real-Time ECG Classification System Using Quantized Inception-ResNeXt Neural Network and CWT Approximation |
| VLSI_2026_28_HS | An Efficient VLSI Architecture for Hammerstein-Type Spline Adaptive Filters |
| VLSI_2026_39_HS | A High-Energy-Efficiency Lightweight BNN Accelerator for Arrhythmia Detection |
| VLSI_2026_48_HS | An Area-Efficient Normal Input/Output Ordered Memory-Based FFT Using an SC Kernel |
| VLSI_2026_50_HS | An IR-UWB Transmitter Using Two-Dimensional Differential Pulse Position Modulation |
| VLSI_2026_52_HS | FPGA Implementation of a Real-Time Parallel Loop-Unrolled DFE for PAM-4 IM/DD Optical Links |
VLSI Design of Image, Video and Audio Processing
| Project Code | Project Title |
|---|---|
| VLSI_2026_02_IM | An Efficient Accelerator for Dehazing Neural Network Based on Physical Perception Model and Cross-Scale Pixel Attention |
| VLSI_2026_07_IM | EDCSSM: Edge Detection With Convolutional State Space Model |
| VLSI_2026_11_IM | Event-Triggered Multi-Kernel Learning-Based Stochastic MPC With Applications in Building Climate Control |
| VLSI_2026_21_IM | An Energy-Efficient Kalman Filter Coprocessor Design for Multiple-Object Tracking Targeting at Video Understanding |
| VLSI_2026_23_IM | AHCO-YOLO: An Algorithm–Hardware Co-Optimization Framework for Energy-Efficient and Real-Time Object Detection on Edge Devices |
| VLSI_2026_43_IM | TEA-SPS: A Tiny and Efficient Architecture for Softmax With Parallelism and Sparsity Adaptability |